Explain the properties of Heat Treatments and applications. Explain the differences between the ICs and their applications in today’s society. EET191_U5_Lecture2revised-ICs.ppt.pptxE

27 Sep Explain the properties of Heat Treatments and applications. Explain the differences between the ICs and their applications in today’s society. EET191_U5_Lecture2revised-ICs.ppt.pptxE

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answer the following and cite your references:

Explain the properties of Heat Treatments and applications.
Explain the differences between the ICs and their applications in today's society.

PROCESSING OF INTEGRATED CIRCUITS

Overview of IC Processing

Silicon Processing

Lithography

Layer Processes Use in IC Fabrication

Integrating the Fabrication Steps

IC Packaging

Yields in IC Processing

Integrated Circuit (IC)

A collection of electronic devices such as transistors, diodes, and resistors that have been fabricated and electrically intraconnected onto a small flat chip of semiconductor material

Silicon (Si) – most widely used semiconductor material for ICs

Less common: germanium (Ge) and gallium arsenide (GaAs)

Levels of Integration in Microelectronics

Integration level Number devices Approx. year

Small scale integration (SSI) 10 ‑ 50 1959

Medium scale integration (MSI) 50 ‑ 103 1960s

Large scale integration (LSI) 103 ‑ 104 1970s

Very large scale integration (VLSI) 104 ‑ 106 1980s

Ultra large scale integration (ULSI) 106 ‑ 108 1990s

Giga scale integration 109 – 1010 2000s

Overview of IC Technology

An integrated circuit chip consists of hundreds, thousands, or millions of microscopic electronic devices

A chip is a square or rectangular flat plate that is about 0.5 mm (0.020 in) thick and typically 5 to 25 mm (0.2 to 1.0 in) on a side

Each electronic device on the chip surface consists of separate layers and regions with different electrical properties combined to perform a particular function

Integrated Circuit

Highly magnified image of an integrated circuit (photo courtesy of Intel Corporation)

Cross section of a transistor in an integrated circuit – feature sizes can be less than 40 nm

Video

Fabrication of Integrated Circuits (Animation)

(https://youtu.be/IjVrkYteNwY)

Chip Manufacturing

(https://youtu.be/bor0qLifjz4)

How an Integrated Circuit is made

(https://youtu.be/ThNW0EqOH7U)

Processing Sequence for Silicon ICs

Silicon processing – sand is reduced to very pure silicon and then shaped into wafers

IC fabrication – processing steps that add, alter, and remove thin layers in selected regions to form electronic devices

Lithography is used to define the regions to be processed on wafer surface

IC packaging – wafer is tested, cut into individual chips, and the chips are packaged

(1) Pure silicon is formed from molten state into ingot and then sliced into wafers; (2) fabrication of integrated circuits on wafer; and (3) wafer is cut into chips and packaged

Sequence in IC Processing

Clean Rooms

Much of the processing of ICs must be carried out in a clean room

Ambiance of a clean room is more like a hospital operating room than a production factory

Cleanliness is dictated by the microscopic feature sizes in an IC, the scale of which continues to decrease each year

Also shown is the size of common airborne particles that can contaminate the IC processing environment

Trends in IC Feature Size

Silicon Processing

Microelectronic chips are fabricated on a substrate of semiconductor material

Silicon accounts for more than 95% of all semiconductor devices produced in the world today

Preparation of silicon substrate (wafers) can be divided into three steps:

Production of electronic grade silicon

Crystal growing

Shaping of Si into wafers

Electronic Grade Silicon

Silicon is one of the most abundant materials in the earth's crust, occurring naturally as silica (e.g., sand) and silicates (e.g., clay)

Principal raw material for silicon is quartzite, which is very pure SiO2

Electronic grade silicon (EGS) is polycrystalline silicon of ultra high purity

Impurities are measured in parts per billion

Crystal Growing

The silicon substrate for microelectronic chips must be made of a single crystal whose unit cell is oriented in a certain direction

Substrate wafers must be cut in a direction that achieves the desired planar orientation

Most widely used crystal growing method is the Czochralski process

A single crystal boule is pulled from a pool of molten silicon

Shaping of Silicon into Wafers

Processing steps to reduce the boule into thin, disc‑shaped wafers

Ingot (boule) preparation

Wafer slicing

Wafer preparation

Preparation of the Boule

The ends of the boule are cut off

Cylindrical grinding is used to shape the boule into a more perfect cylinder

One or more flats are ground along length of boule

(a) Cylindrical grinding provides diameter and roundness control and (b) a flat ground on the cylinder

Wafer Slicing

Cutting edge is a very thin ring-shaped saw blade with diamond grit on internal diameter

ID used for slicing rather than the OD for better control over flatness, thickness, parallelism, and surface characteristics of the wafer

Wafers are cut  0.5‑0.7 mm (0.020‑0.028 in.) thick, greater thicknesses for larger wafer diameters

To minimize kerf loss, blades are very thin: thickness ~ 0.33 mm (0.013 in)

Wafer slicing using a diamond abrasive cut‑off saw

Wafer Preparation

Wafer rims are rounded by contour‑grinding wheel to reduce chipping during handling

Wafers are chemically etched to remove surface damage due to slicing

A flat polishing operation is performed to provide surfaces of high smoothness for photolithography processes to follow

Finally, wafer is chemically cleaned to remove residues and organic films

Lithography

An IC consists of many microscopic regions on the wafer surface that make up the devices and intraconnections as specified in the circuit design

In the planar process, regions are fabricated by steps that add, alter, or remove layers in selected areas of the wafer surface

Each layer is determined by a geometric pattern representing circuit design information that is transferred to the wafer surface by lithography

Lithographic Technologies

Several lithographic technologies are used in semiconductor processing:

Photolithography

Electron lithography

X‑ray lithography

Ion lithography

The differences are in type of radiation used to transfer the mask pattern to the wafer surface

Photolithography

Uses light radiation to expose a coating of photoresist on the surface of the wafer

Common light source in wafer processing is ultraviolet light, due to its short wavelength

A mask containing the required geometric pattern for each layer separates the light source from the wafer, so that only the portions of the photoresist not blocked by the mask are exposed

Photolithography Mask

Flat plate of transparent glass onto which a thin film of an opaque substance has been deposited in certain areas to form the desired pattern

Thickness of glass plate is around 2 mm (0.080 in), while deposited film thickness is only ~ 1 m

The mask itself is fabricated by lithography

The pattern is based on circuit design data, usually the digital output from a CAD system used by circuit designer

Photoresist

Organic polymer that is sensitive to light radiation in a certain wavelength range

Sensitivity causes either increase or decrease in solubility of the polymer to certain chemicals

Typical practice in semiconductor processing is to use photoresists that are sensitive to UV light because of its shorter wavelength

Also permits fabrication areas in plant to be illuminated at low light levels outside UV band

Photolithography Exposure Techniques

(a) Contact printing, (b) proximity printing, (c) projection printing

Photolithography Processing Sequence

Surface of the silicon wafer has been oxidized to form a thin film of SiO2

It is desired to remove the SiO2 film in certain regions as defined by mask pattern

Sequence for a negative resist proceeds as follows:

Photolithography Processing Sequence

(1) Prepare surface, (2) apply resist, (3) soft bake, (4) align mask and expose, (5) develop resist, (6) hard bake, (7) etch, (8) strip resist

A partially processed silicon wafer after several lithography steps (courtesy of George E. Kane Manufacturing Technology Laboratory, Lehigh University)

Other Lithography Techniques

As feature sizes in integrated circuits continue to decrease and UV photolithography becomes increasingly inadequate, other lithography techniques that offer higher resolution are growing in importance

Extreme ultraviolet (EUV) lithography

Electron beam lithography

X‑ray lithography

Ion lithography

Layer Processes Used in IC Fabrication

Steps to fabricate ICs on a silicon wafer consist of chemical and physical processes that add, alter, or remove regions defined by photolithography

Regions are insulating, semiconducting, and conducting areas that form the devices and their intraconnections in the IC

Layers are fabricated one at a time, each layer requiring a separate mask, until all of the details have been fabricated onto the wafer surface

Layering Processes in IC Fabrication

Thermal oxidation – adds SiO2 layer on Si substrate

Chemical vapor deposition – adds various layers

Diffusion and ion implantation – alter chemistry of an existing layer or substrate

Metallization processes – add metal layers for electrical conduction

Etching processes – remove portions of layers to achieve desired IC details

Thermal Oxidation of Silicon

Exposure of silicon wafer surface to an oxidizing atmosphere at elevated temperature to form layer of silicon dioxide

Oxygen or steam atmospheres are used, with the following reactions, respectively:

Si + O2  SiO2

Si + 2H2O  SiO2 + 2H2

Growth of SiO2 film on a silicon substrate by thermal oxidation, showing changes in thickness that occur: (1) before oxidation and (2) after thermal oxidation

Functions of Silicon Dioxide

SiO2 is an insulator, compared to Si which is a semiconductor

Used as a mask to prevent diffusion or ion implantation of dopants into silicon

Can be used to isolate devices in circuit

Provides electrical insulation between levels in multi‑level metallization systems

Alternative Process for Adding SiO2

When a silicon dioxide film must be applied to surfaces other than silicon, then direct thermal oxidation does not work

An alternative process must be used, such as chemical vapor deposition

Introduction of Impurities into Silicon

IC technology relies on the ability to alter the electrical properties of silicon by introducing impurities into selected regions of the surface

Called Doping – adding impurities into Si surface

Common doping elements are boron (B), phosphorous (P), arsenic (As), and antimony (Sb)

Techniques for doping silicon:

Thermal diffusion

Ion implantation

Thermal Diffusion

Process in which atoms migrate from regions of high concentration into regions of lower concentration

In semiconductor processing, diffusion is carried out to dope the silicon substrate with controlled amounts of a desired impurity

Two steps in thermal diffusion:

Predeposition – dopant is deposited onto wafer

Drive‑in – heat treatment in which dopant is redistributed to obtain desired depth and profile

Ion Implantation

Vaporized ions of impurity element are accelerated by an electric field and directed at silicon substrate

Atoms penetrate into surface, losing energy and finally stopping at some depth in crystal structure determined by mass of ion and acceleration voltage

Advantages:

Can be accomplished at room temperature

Provides exact doping density

Metallization

Combines various thin film deposition technologies with photolithography to form very fine patterns of conductive material

Functions of conductive materials on wafer surface:

Form certain components (e.g., gates) of IC devices

Provide intraconnecting conduction paths between devices on chip

Connect the chip to external circuits

Metallization Materials

Aluminum – most widely used metallization material

Favored for device intraconnections and connections to external circuitry

Other materials: polysilicon (Si); gold (Au); refractory metals (e.g., W, Mo); silicides (e.g., WSi2, MoSi2, TaSi2); and nitrides (e.g., TaN, TiN, and ZrN)

Applications such as gates and contacts

Metallization Processes

Physical vapor deposition – PVD metallization processes include vacuum evaporation and sputtering

Chemical vapor deposition – CVD deposited materials include tungsten, molybdenum, and most silicides used in semiconductor metallization

Electroplating – occasionally used to increase thickness of thin films

Etching

Certain steps in IC manufacturing require material removal from surface, accomplished by etching away unwanted material

Usually done selectively, by masking areas that are to be protected and leaving other areas exposed

Two categories of etching process:

Wet chemical etching

Dry plasma etching

Wet Chemical Etching

Use of an aqueous solution, usually an acid, to etch away a target material

Etchant is selected to chemically attack the specific material and not the protective layer

Process variables are immersion time, etchant concentration, and temperature

In its simplest form, etching involves immersing the masked wafers for a specified time and then immediately rinsing to stop the etching

Chemical etching reaction is isotropic, causing an undercut below protective mask

Mask pattern (resist) must be sized to compensate

Profile of a properly etched layer shown below

Chemical Etching

Process Integration in IC Fabrication

An n‑channel metal oxide semiconductor (NMOS) logic device will be used to illustrate processing sequence

Starting substrate is a lightly doped p‑type silicon wafer, which will form the base of n‑channel transistor

IC Fabrication Sequence

Si3N4 mask is deposited by CVD on Si substrate, (2) SiO2 is grown by thermal oxidation in unmasked regions, (3) Si3N4 mask is stripped, (4) thin layer of SiO2 is grown by thermal oxidation

IC Fabrication Sequence

(5) Polysilicon is deposited by CVD and doped n+ using ion implantation, (6) poly-Si is selectively etched using photo-lithography to define gate electrode, (7) source and drain regions are formed by doping n+ in substrate, (8) P-glass is deposited onto surface for protection

IC Packaging

Final series of operations to transform the wafer into individual IC chips

(Accomplished after all of the processing steps on the wafer have been completed )

To connect the IC to the outside world, and to protect it from damage, the chip is attached to a lead frame and encapsulated inside a suitable package

The package is an enclosure, made of plastic or ceramic, that provides mechanical and environmental protection for the chip

The package includes leads by which the IC can be electrically connected to external circuits

Design Issues in IC Packaging

Electrical connections to external circuits

Materials to encase chip and protect it from the environment

Humidity and corrosion

Temperature

Vibration and mechanical shock

Heat dissipation

Performance, reliability, and service life

Cost

Manufacturing Issues in IC Packaging

Chip separation ‑ cutting wafer into individual chips

Connecting it to the package

Encapsulating the chip

Circuit testing

IC Package Design

Factors related to the design of an integrated circuit package:

Number of input/output terminals required for an IC of a given size

Materials used in IC packages

Package styles

Input/Output (I/O) Terminals

Problem is to connect many internal circuits on the chip to I/O terminals so that the appropriate electrical signals can be communicated to the outside world

As the number of devices in the IC increases, the required number of I/O terminals also increases

The problem is aggravated by IC trends:

Decreases in device size

Increases in number of devices in IC

IC Package Materials

Ceramic (Al2O3)

Advantages: hermetic sealing of IC chip and highly complex packages can be produced

Disadvantage: poor dimensional control due to shrinkage during firing

Plastic (epoxies, polyimides, and silicones)

Not hermetically sealed, but cost is lower

Generally used for mass produced ICs, where very high reliability is not required

Two Basic Types of IC Package

Through‑hole mounting, also called pin‑in‑hole (PIH) technology

IC package and other components have leads inserted through holes in PCB and soldered on underside

Surface mount technology (SMT)

Components are attached to surface of board (in some cases, both top and bottom surfaces)

Types of component lead attachment on a printed circuit board: (a) through‑hole, and several styles of surface mount technology: (b) butt lead, (c) "J" lead, and (d) gull‑wing

Two Basic Types of IC Package

Major IC Package Styles

Dual in‑line package (DIP)

Square package

Pin grid array

Some of these are available in both through‑hole and surface mount styles, while others are designed for only one mounting method

(a) Dual in‑line package with 16 terminals, shown here in through‑hole configuration and (b) square leaded chip carrier (LCC) for surface mounting with gull wing leads

(a) (b)

Dual In-Line Package (DIP)

Processing Steps in IC Packaging

Wafer testing

Chip separation

Die bonding

Wire bonding

Package sealing

Final testing

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27 Sep Explain the properties of Heat Treatments and applications. Explain the differences between the ICs and their applications in today’s society. EET191_U5_Lecture2revised-ICs.ppt.pptxE

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