27 Sep Reduced Instruction Set Computers

Discussion 4 – RISC requirements

200-250 words

Please read the following and answer the questions at the end.

Reduced Instruction Set Computers

A reduced instruction set computer (RISC) is a type of microprocessor architecture that has applied the following architectural changes to the organization of a processor to improve its computing performance:

• A RISC’s instruction set only has a limited number of instructions.

• A RISC’s CPU accesses the memory and input/output (I/O) devices through separated data communication buses, which allows for more parallel computing. This is in contrast to a conventional processor architecture, where the CPU, memory, and I/O devices all share the same data communication bus.

• A RISC’s CPU can execute most instructions in one clock cycle.

Review this detailed introduction to the concepts of a RISC.

A RISC is very efficient due to its ability to execute most instructions in one clock cycle, which is a feature that sets it apart from non-RISC computers, which require multiple clock cycles to execute one instruction. These non-RISC computers are known as complex instruction set computers (CISCs).

The following table summarizes the differences between RISCs and CISCs (Ahlawat, 2021):

Architectural Characteristics Complex Instruction Set Computers Reduced Instruction Set Computer

Instruction size and format Large set of instructions with variable formats (16–64 bits per instruction) Small set of instructions with fixed format (32-bit)

Data transfer Memory to memory Register to register

CPU control Mostly microcoded using control memory (read-only memory [ROM]); modern CISCs use hardwired controls Mostly hardwired without control memory

Instruction type Nonregister-based instructions Register-based instructions

Memory access More memory access Less memory access

Clocks Includes multiclock complex instructions Single-clock; reduced instructions only

Instruction nature Complex instructions Reduced and simple instructions

Flynn’s Taxonomy: Multiprocessing and Parallel Processing Computer Architectures

One strategy to improve the performance of a computer is using a parallel architecture, which introduces parallel computing into the computer architecture.

Flynn’s taxonomy was created to classify the different types of parallel architectures.

Flynn’s taxonomy is a classification of computing systems proposed by Michael Flynn. The basic idea of the classification is that computer programs are composed of two streams: data stream and task (or instructional) stream. This gives the possibility of four combinations depending on the streams being serial (single stream) or parallel (multiple streams). (GeeksforGeeks, 2020)

The following diagram shows all of the possible parallel computing architectures (GeeksforGeeks, 2020):

The following table discusses the different types of parallel architectures (Flynn’s Architecture Taxonomy, 2018):

Type of Parallel Computing Architecture Description

Single instruction, single data (SISD) This architecture represents a classic, traditional computing system and executes one program (instruction stream) on one set of data (data stream). This matches a program that is written using a procedural programming language and is executed on one single-core CPU.

Single instruction, multiple data (SIMD) This is one of the most commonly used parallel architectures due to its efficiency. In this architecture, one program is written, and different copies of this programs run on different CPUs (or cores). In the SIMD architecture, synchronization must be achieved at the instruction level. In other words, at a certain moment, the same instruction should run on all processors, and each processor should execute this instruction on the data that it has.

Multiple instruction, single data (MISD) Hardware-wise, this is not a very common architecture. Algorithmically, this architecture is used when you want to apply or test different algorithms on the same data set, such as when you want to apply different graphics filters to the same image.

Multiple instruction, multiple data (MIMD) This is the most general architecture. In this architecture, different instructions can run over different sets of data. Recently, all multicore CPUs are considered MIMDs because they can be programmed with different instruction streams (programs), with each stream running on its own data on its own core (ideally).

Assignment Details

Assume that two students have been assigned the task of selecting a computer for a family doctor’s office. Student A has selected a reduced instruction set computer (RISC), while student B proposed to use a multiprocessor computer. Student A’s assumption is that the doctor’s office does not have enough complicated tasks to require a device that has multiprocessors and supports multiprocessing and parallel processing. Student B’s assumption is the opposite; the family doctor’s office will often need to support multiple tasks, such as printing bills, receiving faxes and e-mails, staying connected to remote sites to access patients’ data through a wide area network (WAN) interface, displaying patients’ X-ray images, supporting the front desk’s patient data entry and appointment management, and billing operations. Student B’s idea is that it is better to have a computer that has multiple central processing units (CPUs) to support multiprocessing and parallel processing so that the doctor’s office can run more efficiently.

Primary Response

Now that you have a better understanding of the basic concepts related to RISCs and Flynn’s taxonomy, you can post your discussion of the following questions and determine which student had the better assumption for the computer system that is needed for the family doctor’s office:

• What are the pros and cons of each type of computer based on each student’s assumption?

• How would you classify these two types of computers based on Flynn’s taxonomy?

Remember, student A selected a RISC computer, while student B proposed a multiprocessor computer. Please review the assumptions made by each of the two students to answer each question thoroughly.